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EXS Node Configuration Query 0x007E

SwitchKit Name

NodeConfigQuery

Type

EXS API and SwitchKit API message

Description

EXS Node Configuration Query 0x007E

Use this message to query various configuration entities in a node.

Sent by

Host

SwitchKit Code

C Structure

typedef struct {

unsigned short Entity;

UBYTE DataLen;

UBYTE Data[250];

} XL_NodeConfigQuery;

C Structure Response

typedef struct {

unsigned short Status;

unsigned short Entity;

UBYTE DataLength;

UBYTE Data[248];

} XL_NodeConfigQueryAck;

C++ Class

class XLC_NodeConfigQuery : public XLC_OutboundMessage {

public:

unsigned short getEntity() const;

void setEntity(unsigned short x);

UBYTE getDataLen() const;

void setDataLen(UBYTE x);

const UBYTE *getData() const;

UBYTE *getData();

void setData(UBYTE *x);

};

C++ Class Response

class XLC_NodeConfigQueryAck : public XLC_AcknowledgeMessage {

public:

unsigned short getStatus() const;

void setStatus(unsigned short x);

unsigned short getEntity() const;

void setEntity(unsigned short x);

UBYTE getDataLength() const;

void setDataLength(UBYTE x);

const UBYTE *getData() const;

UBYTE *getData();

void setData(UBYTE *x);

};

EXS API Hex Format

MESSAGE (White) | RESPONSE (Gray)
Byte | Field Description | Byte | Field Description
0 | Frame (0xFE) | 0 | Frame (0xFE)
1, 2 | Length (0xNNNN) | 1, 2 | Length (0xNNNN)
3, 4 | Message Type (0x007E) | 3, 4 | Message Type (0x007E)
5 | Reserved (0x00) | 5 | Reserved (0x00)
6 | Sequence Number | 6 | Same Sequence Number
7 | Logical Node ID | 7 | Logical Node ID
8, 9 | Entity MSB, LSB 0x0001 Number of Timeslots 0x0002 Reserved 0x0004 Clock Master 0x0005 Master on Multiple Ring Configure 0x0006 - CTNETREF | 8, 9 | Status (MSB, LSB)
10 | Data Length | 10, 11 | Entity (MSB, LSB)
12 | Data Length
11 | Data 0x01 Number of Timeslots Data[0,1] Number of Timeslots assigned for CSP Conferencing (Enter 0xFFFF to assign all unused timeslots) | 13 | Data 0x01 Number of Timeslots Data[0,1] Number of timeslots assigned Data[2,3] Number of timeslots that are actually allocated
|  | 14 | Checksum
| 0x04 Clock Master Data[0] Slot Number Data[1] Configured Bus Master 0x00 PCI H.100 EXNET Connect is configured to be slave to clock A of H.100 local bus. 0x01 H.100 primary clock master driving clock A PCI H.100 EXNET Connect is configured to be H.100 local bus master driving clock A. 0x02 H.100 secondary clock master driving clock. This is clock A. 0x03 H.100 slave to clock B 0x04 H.100 primary clock master driving clock B 0x05 H.100 secondary clock master driving clock B Data[2] Configured Speed 0x00 4 MHz [SCSA compatibility mode] EXNET Connects are configured at this bus speed. Lower 16 data lines of H.100 bus are configured at this bus speed. 0x02 8 MHz [Full H.100 mode] All 32 data lines of H.100 bus are configured at this bus speed. Data[3] Actual Bus Master 0x00 H.100 Slave to clock A. EXNET Connect actual state is not as local bus master. PCI H.100 EXNET Connect actual state is slave to clock A of H.100 local bus. 0x01 H.100 primary clock master driving clock. A PCI H.100 EXNET Connect actual state is H.100 local bus master driving clock A. 0x02 H.100 secondary clock master driving clock A 0x03 H.100 slave to clock B 0x04 H.100 primary clock master driving clock B 0x05 H.100 secondary clock master driving clock B 0x06 H.100 bus not available Data[4] Actual Speed 0x00 4 MHz [SCSA compatibility mode] EXNET Connects are at this bus speed. Lower 16 data lines of H.100 bus are at this bus speed. 0x02 8 MHz [Full H.100 mode] All 32 data lines of H.100 bus are at this bus speed.
| 0x05 Master On Multiple Ring Configure The value of this field indicates whether or not a node is allowed to become the EXNET® Master of multiple rings. Data[0] Master on Multiple Ring Flag 0x00 Do not allow this node to be Master on more than one ring simultaneously (Default) 0x01 Allow this node to be Master on more than one ring simultaneously.
| 0x06 CTNETREF Data[0] Slot Number (Indicates slot number of the board that is queried.) Data[1] CTNETREF Drive/Receive 0x00 Receive. Indicates the board is configured to receive the CTNETREF signal from other boards on the H.100 bus. 0x01 Drive Data[2] CTNETREF Speed 0x00 - 2.048 MHz 0x01 - 1.54 MHz 0x02 - 8 kHz
: | Checksum

A computer, attached to the Excel platform through an RS-232 or Ethernet link, from which you run the telecommunications application that controls the Excel platform.
A group of data bits in a specific format, with a flag at each end to indicate the beginning and the end of the frame.
Most Significant Bit
Least Significant Bit
Peripheral Component Interconnect
Excel's open architecture, proprietary, 1.3 Gbps fiber optic network using a packet-based protocol.
See Signal Computing System Architecture.
Message delimiter (SS7 bit pattern - 01111110)