# DSP resources

CG board DSP resource usage is calculated based on the following categories:

- MIPS

- Memory

- Timeslots

- Packet queues

- Buffer size

Each DPF that executes on a DSP core consumes resources from each of these categories. The overall resource usage dictates how many DPFs can run on a DSP core, and consequently how many ports can run per board. The following table describes these resource categories:

Resource category | Description
--- | ---
MIPS | Measures the computational capacity of a DSP core and the fraction of a DSP core's processing power consumed by a given DPF. Each DSP core on a CG board runs at 133 MIPS. The DSP operating system (DSPOS) consumes approximately 5 MIPS, leaving approximately 128 MIPS per DSP core available for the loadable DPFs.
Memory | Each DSP core has a total of four DSP cores arranged as two core pairs. Each core pair has 128 K of shared program memory and 64 K of data memory.
Timeslots (input and output) | Each DSP core is connected to an H.110 (H.100 for CG 6000) interface chip through shared local streams consisting of 128 input and 128 output timeslots. Groups of four DSP cores are connected to a single local stream. Therefore, each DSP core in the group is physically connected to 128 input and output timeslots. However, each DSP uses only a subset of the available timeslots. The DSP operating system supports 16 or 32 full duplex timeslots per DSP core. Input timeslots on CG boards can be shared between DPFs. In addition, there are 32 input and 32 output timeslots internal to each DSP core. These internal timeslots are used for DPF-to-DPF communication.
Packet queue (input and output) | Carries data between the DSP cores and the CG board processor. The number of queues is limited in the DSP operating system to conserve system memory and optimize performance.
Buffer size | Packets and buffers take up resources in the DSP-to-coprocessor buffer or coprocessor-to-DSP buffer.

The following table summarizes resources available on each CG board DSP core:

Resource category | Available resource
--- | ---
MIPS | Approximately 128 MIPS per DSP
External timeslots (input and output) | 16 or 32 full duplex
Internal timeslots (input and output) | 32 in and 32 out
Memory | Approximately 64 K words
Input packet queues | 64
Output packet queues | 64
Buffer size (coprocessor-to-DSP and DSP-to-coprocessor) | 768 words each