# H.100/H.110 clocking overview

When multiple boards are connected to the CT bus, you must set up a bus clock to synchronize timing between them. In addition, you can configure alternative (or fallback) clock sources to provide the clock signal if the primary source fails.

This topic provides a brief overview of CT bus clocking, including clock references and clock fallback.

For more information about clocking, refer to the NMS OAM System User's Manual.

Caution: | NMS strongly recommends that you do not mix H.100 or H.110 systems with MVIP systems when using clock fallback.

Boards in a CT bus system can be configured in any of the following modes:

Board mode | Description
--- | ---
Primary clock master | Drives the primary timing reference for boards connected to the CT bus. It can switch between two specified timing sources to maintain the primary timing reference. However, if both timing references fail, the primary master stops providing a timing source. The secondary master then provides bus synchronization.
Secondary clock master | Drives the secondary timing reference. When the primary clock fails, the secondary master continues to drive the secondary clocks using a clock fallback source as its timing reference.
Clock slave | References it's timing from the primary clock master and uses the secondary clock master as a fallback source of clock timing.
Standalone | Does not reference the primary or secondary master and, consequently, cannot make switch connections to the CT bus.

Some board models have more flexible and reliable clocking capabilities than others. In a mixed board system, choose the boards with the best capabilities as your primary master and secondary master. To determine which boards to use as masters, refer to the NMS OAM System User's Manual.

## Clock references

Boards that act as clock slaves derive their timing from signals driven by the clock masters (primary or secondary). Clock masters can drive the following reference clocks:

- A_CLOCK

- B_CLOCK

Primary clock masters can synchronize their own timing signals from the following sources:

- NETWORK

- NETREF

- OSC

Secondary clock masters are hybrid systems. Their primary timing source must be A_CLOCK or B_CLOCK. Their fallback timing source must be one of the following sources:

- NETWORK

- NETREF

- OSC

## Clock fallback

The CT bus supports a clock fallback mechanism that allows the system to use alternate timing references when one or more sources fail. To enable clock fallback, set the Clocking.HBus.ClockMode keyword to Yes. If you do not enable clock fallback, the application must perform all clocking tasks.

Follow these steps to implement clock fallback:

Step | Action
1 | Configure a primary clock master to drive the CT bus clock (A_CLOCK or B_CLOCK) based on a network timing reference. All slave boards synchronize their timing through this clock.
2 | Configure a secondary clock master to use the signal from the primary clock to drive the alternate CT bus clock. In other words, if the primary master drives the A_CLOCK, configure the secondary master to drive the B_CLOCK based on the A_CLOCK, or vice versa.
3 | Specify a fallback network timing reference for the secondary clock master to use if the primary clock master fails.
4 | Configure all slave boards to specify the secondary clock master as their clock fallback source.

When the boards are configured in this way, the secondary clock master continues to drive the secondary clock (based on its own timing reference) if the primary clock master fails. Slave boards within the system fall back to synchronize their timing from the secondary clock master.