# Board-level clock fallback behavior

This topic describes the following aspects of clock fallback behavior when clocking is configured with board keywords:

- Primary clock master fallback behavior

- Secondary clock master fallback behavior

- Clock slave fallback behavior

Note: The illustrations describe the actions taken by most NMS board models in these situations. For specifics on a particular board, refer to the board manual.

## Primary clock master fallback behavior

The following illustration shows the role of the primary clock master in board-level clock fallback. If the primary master loses its primary timing reference and switches to its secondary reference, and then the primary reference is established again, the master switches back to the primary timing reference. The following illustration show clock fallback behavior for the primary clock master:

## Secondary clock master fallback behavior

The following illustration shows the role of the secondary clock master in board-level clock fallback. The secondary master takes over when the primary master stops driving the clock. The secondary master continues to drive the clock for the system until an application intervenes. The following illustration show clock fallback behavior for the secondary clock master:

## Clock slave fallback behavior

If the primary master stops driving the clock, all slaves attempt to switch over to the other CT bus clock, driven by the secondary master. They continue to use this clock until reset by an application.

If fallback is enabled, but the secondary timing reference is not functional, the board enters standalone mode, using its internal oscillator as the timing reference. It continues in this fashion until the secondary timing reference is restored. The board continues using either the secondary timing reference or the oscillator until reset by an application.

For more information, refer to the illustration in Primary clock master fallback behavior.