# Fallback timing references

Boards can optionally be assigned a backup (fallback) timing reference that it can use if its primary timing reference fails. For a clock master, the source for the fallback timing reference should NOT be the source currently used by the clock master for its primary timing reference.

For example, if a clock master's primary timing reference source is a NETWORK signal from one of its trunks, the fallback timing reference source can be a NETWORK signal from another one of its trunks, or a signal from NETREF1, NETREF2 (if H.110), or OSC. In the following illustration, the fallback timing reference source is NETREF1. The following illustration shows a system using a fallback timing reference:

The ability of a board to automatically switch to its fallback timing reference if its primary timing reference fails is called clock fallback. This feature can be enabled or disabled.

Note: Not all boards support clock fallback. For more information about board models, refer to the board documentation.

## Secondary clock masters

You can set up a second device to be used as a backup, or secondary clock master, if the primary clock master stops driving its CT bus clock (because both of its timing references failed, or it was hot swapped out, or for some other reason). For the secondary clock master to work:

1. It must receive its primary timing reference from the CT bus clock driven by the primary clock master (either A_CLOCK or B_CLOCK).

2. It must drive the CT bus clock not driven by the primary master. For example, if the primary clock master is driving A_CLOCK, the secondary clock master must drive B_CLOCK. In this case, both clocks are synchronized.

3. It must have a fallback timing reference. This timing reference must not be the primary clock master's primary or fallback timing reference.

4. All other slave boards must be set up so their fallback timing references are the CT bus clock driven by the secondary clock master.

The following illustration shows a sample secondary clock master configuration:

Note: Not all boards can act as secondary master. For information about the boards, refer to the board-specific documentation.

With a secondary clock master, clock fallback works as follows:

1. As long as the primary clock master is driving its CT bus clock, the secondary clock master acts as a slave to the primary clock master. However, the secondary master also drives the CT bus clock not driven by the primary master (for example, B_CLOCK if the primary master is driving A_CLOCK).

2. If the primary clock master stops driving its CT bus clock, all slaves (including the secondary clock master) lose their primary timing reference.

3. This triggers the secondary master to fall back to its fallback timing reference.

4. This also triggers other slaves to fall back to the CT bus clock driven by the secondary clock master.

5. The secondary master and slaves do not switch back to the primary timing reference automatically if the primary reference is re-established. Software intervention is required prior to any further clock changes.

6. If the board formerly used as the primary clock master is still active but is not receiving a primary or fallback timing reference, the board attempts to become a slave to the clock driven by the secondary master.

The secondary clock master is now clock master for the whole system. The following illustration shows the secondary clock master driving system clock: