# H.110 clock configuration example

In this example, there are four NMS CompactPCI boards in the system. The first board is the primary master that drives the H.110 A clock from the PSTN network connection. The second board is the secondary master that drives the H.110 B clock from the H.110 A clock. The second board uses a PSTN network connection as an alternate clock source when a fallback to the B clock occurs. The third board drives the NETREF_1 signal from its own PSTN network connection. The fourth board drives the NETREF_2 signal from its own PSTN network connection.

If the primary clock master fails, fallback to a secondary master (B clock) can be programmed to be automatic. In this example, the secondary master uses its own PSTN interface to drive the B clocks. The secondary master can also be programmed to use either of the NETREF signals if so desired.

Note: This example is applicable to the NMS CompactPCI AG, CG, and CX boards.

This example:

- Configures the board clock
  of the first CompactPCI board to synchronize to the PSTN clocks and become the H.110 A clock master.

- Configures the board clock of the second CompactPCI board to synchronize to the A clocks and become the H.110 B clock master. Its fallback source is its network connection.

- Configures the third and fourth boards to slave off the A clocks.

- Configures the third and fourth boards to drive NETREF_1 and NETREF_2 respectively.

- Sets the automatic fallback feature to allow for a fallback from the primary to the secondary master.

For information about configuring the clock fallback feature, refer to the NMS OAM System User's Manual. For more information about H.110 A clocks and B clocks, refer to the ECTF: H.110 Revision 1.0 Hardware Compatibility Specification: CT Bus.

The following illustration shows the example of clock fallback:

1. Configure the board clock of the first CompactPCI board to synchronize to the PSTN clocks and become the primary clock master (A clock).

SWI_CLOCK_ARGS boardclock;
/* Make first board sync off the PSTN digital trunk 1 */
boardclock.size = sizeof(SWI_CLOCK_ARGS);
boardclock.clocktype = MVIP95_H100_CLOCKING;
boardclock.clocksource = MVIP95_SOURCE_NETWORK;
boardclock.network = 1;
boardclock.ext.h100.h100clockmode= MVIP95_H100_MASTER_A;
boardclock.ext.h100.autofallback= MVIP95_H100_ENABLE_AUTO_FB;
boardclock.ext.h100.netrefclockspeed= MVIP95_H100_NETREF_8KHZ;
boardclock.ext.h100.fallbackclocksource= MVIP95_SOURCE_NETWORK;
boardclock.ext.h100.fallbacknetwork = 2;
swiConfigBoardClock(firstt1, &boardclock);

2. Configure the board clock of the second CompactPCI board to synchronize to the PSTN clocks and become the secondary clock master (B clock).

SWI_CLOCK_ARGS boardclock;
boardclock.size = sizeof(SWI_CLOCK_ARGS);
boardclock.clocktype = MVIP95_H100_CLOCKING;
boardclock.clocksource = MVIP95_SOURCE_H100_A;
boardclock.network = 0;
boardclock.ext.h100.h100clockmode= MVIP95_H100_MASTER_B;
boardclock.ext.h100.autofallback= MVIP95_H100_ENABLE_AUTO_FB;
boardclock.ext.h100.netrefclockspeed= MVIP95_H100_NETREF_8KHZ;
boardclock.ext.h100.fallbackclocksource= MVIP95_SOURCE_NETWORK;
boardclock.ext.h100.fallbacknetwork = 1;
swiConfigBoardClock(secondt1, &boardclock);

3. Configure the board clocks of the third and fourth CompactPCI boards to slave to the H.110 A clocks.

SWI_CLOCK_ARGS boardclock3;
SWI_CLOCK_ARGS boardclock4;
boardclock3.size = sizeof(SWI_CLOCK_ARGS);
boardclock3.clocktype = MVIP95_H100_CLOCKING;
boardclock3.clocksource = MVIP95_SOURCE_H100_A;
boardclock3.network = 0;
boardclock3.ext.h100.h100clockmode= MVIP95_H100_SLAVE;
boardclock3.ext.h100.autofallback= MVIP95_H100_ENABLE_AUTO_FB;
boardclock3.ext.h100.netrefclockspeed= MVIP95_H100_NETREF_8KHZ;
boardclock4.size = sizeof(SWI_CLOCK_ARGS);
boardclock4.clocktype = MVIP95_H100_CLOCKING;
boardclock4.clocksource = MVIP95_SOURCE_H100_A;
boardclock4.network = 0;
boardclock4.ext.h100.h100clockmode= MVIP95_H100_SLAVE;
boardclock4.ext.h100.autofallback= MVIP95_H100_ENABLE_AUTO_FB;
boardclock4.ext.h100.netrefclockspeed= MVIP95_H100_NETREF_8KHZ;
swiConfigBoardClock(thirdt1, &boardclock3);
swiConfigBoardClock(fourtht1, &boardclock4);

4. Configure the third and fourth CompactPCI boards to drive the NETREF_1 and NETREF_2 signals on the H.110 bus from their PSTN connection.

SWI_NETREF_CLOCK_ARGSnetref_1;
SWI_NETREF_CLOCK_ARGSnetref_2;
netref_1.size = sizeof(SWI_NETREF_CLOCK_ARGS);
netref_1.network = 1;
netref_1.netref_clock_mode = MVIP95_H100_NETREF_1;
netref_1.netref_clock_speed = MVIP95_H100_NETREF_8KHZ;
netref_2.size = sizeof(SWI_NETREF_CLOCK_ARGS);
netref_2.network = 1;
netref_2.netref_clock_mode = MVIP95_H100_NETREF_2;
netref_2.netref_clock_speed = MVIP95_H100_NETREF_8KHZ;
swiConfigNetrefClock(thirdt1, netref_1);
swiConfigNetrefClock(fourtht1, netref_2);