# Clock masters and clock slaves

To synchronize data transfer from device to device across the H.100 bus or H.110 bus, devices on the bus must be phase-locked to a high-quality 8 MHz clock and 8 kHz frame pulse. These signals together compose a CT bus clock.

One board on the bus generates (drives) the clock. This board is called the clock master. All other boards use this clock as a timing reference by which they synchronize their own internal clocks. These boards are called clock slaves (see the following illustration).

Note: Not all boards can serve as clock masters. For more information, refer to the board documentation.

The following illustration shows a clock master and clock slaves:

Two CT bus clocks can run simultaneously on the bus. They are called A_CLOCK and B_CLOCK. The clock master can drive either one. When you set up CT bus clocking, choose one of these clocks for your master and slaves. The other one is a redundant signal that can be used by a secondary clock master. Refer to Secondary clock masters for more information.

The following illustration shows a system using A_CLOCK as its clock reference: